DESIGN AND ANALYSIS OF LOW-LEAKAGE SRAM CELL IN SUB-30 NM CMOS TECHNOLOGY A COMPREHENSIVE REVIEW

Abstract

As CMOS devices are moving into a range of less than 30 nm, leakage power has become a major issue for static random-access memory (SRAM) design. The SRAM blocks consume a significant area of modern system-on-chip designs, which are always active even during idle mode. This makes them more prone to leakage currents. This review paper aims to provide a detailed discussion on leakage issues for sub-30 nm CMOS devices, a thorough review of various low leakage techniques for designing static random-access memory, static noise margin, data retention voltage, read/write margins, process variations, supply voltage scaling, and temperature variations. In addition, a practical approach to designing a low leakage SRAM cell using conventional techniques is also explored. The aim is to provide a clear review of previously published research on low leakage techniques for designing static random-access memory while making connections between theoretical principles and practical considerations used during modern static random access memory design [1], [8].